1. Field of the Invention
The present invention relates to a flash memory cell and method of fabrication, and more particularly, to an electron tunnel oxide (ETOX) flash memory cell and method of fabricating the same.
2. Description of the Prior Art
Please refer to FIG. 1, which is a cross-sectional view illustrating a conventional flash memory cell 3. As shown in FIG. 1, the method of fabricating the conventional flash memory cell 3 is to first form a tunnel oxide layer 31, a floating gate layer 32, a dielectric layer 33, and a control gate layer 34 on a substrate 30 in sequence. Then a photolithography process is performed to form a stacked gate by utilizing a mask. An ion implantation process is thereafter performed to form a source 36 and a drain 35 in the substrate 30.
When the flash memory cell 3 is working, a voltage level of 10–12V needs to be applied to the source 36. In order to sustain such a high voltage, the junction of the source 36 and the substrate 30 should be a deep junction. According to the diffusion theory, a lateral width (sector a) of the source 36 is large. Therefore a band to band tunneling phenomenon occurs when the above-mentioned high voltage is applied to the source 36. In other words, holes readily flow into the floating gate layer 32 when the above-mentioned high voltage is applied to the source 36, leading to the degradation of the tunnel oxide layer 31. The deep junction also results in leakage current flowing into the substrate 30 and increases the impedance of the power supply. In addition, the unit area of the flash memory cell 3 is unable to be shrunk because of the large lateral width of the source 36, providing limitation to miniaturizing.
Please refer to FIG. 2, which is a cross-sectional view illustrating another conventional flash memory cell 4. As shown in FIG. 2, the method of fabricating the conventional flash memory cell 4 is to first form a tunnel oxide layer 41, a floating gate layer 42, a dielectric layer 43, and a control gate layer 44 on a substrate 40 in sequence. Then a photolithography process is performed to form a stacked gate by utilizing a mask. After that, deposition and etching processes are performed to form a polysilicon spacer 45 (an erasing gate layer) at either side of the stacked gate. The polysilicon spacer 45 is separate from the stacked gate and the substrate 40 with an erasing oxide layer 46 in between.
During an erasing operation of the flash memory cell 4, electrons flow from the floating gate layer 42 to the polysilicon spacer 45 (the erasing gate layer) through the erasing oxide layer 46. At this time, the voltage level applied to the erasing gate layer 45 is usually increased to higher than 15V to discharge the electrons in the floating gate layer 42 by utilizing the potential difference between the erasing gate layer 45 and the floating gate layer 42. According to the prior art method, the erasing oxide layer 46 is formed by a deposition process and thus has a uniform thickness. If the easing oxide layer 46 is too thick, electrons cannot flow through the erasing oxide layer 46 to affect the erasing performance; if the erasing oxide layer 46 is too thin, a breakdown phenomenon is incurred to cause the flash memory cell 4 to not work properly.
It is therefore very important to develop a flash memory and method of fabrication to resolve the above-mentioned problems.